Why Silicon Photonics Could Become the Next AI Data Center Bottleneck

Optical fibers carrying AI data from a silicon photonics chip

Imagine buying thousands of the fastest AI accelerators in the world.

Now imagine many of them spending part of their time waiting for data from other accelerators.

A fast GPU connected by an inadequate network can still become a waiting GPU.

At large scale, AI is not only a computation problem. It is also a data-movement problem.

First, What Is Silicon Photonics?

Fiber is the glass path that carries light.

A laser creates the light source.

An optical transceiver converts electrical data into optical signals and converts incoming light back into electrical data.

A photonic integrated circuit (PIC) puts optical functions such as modulation, routing or detection onto a chip.

Silicon photonics uses silicon-based semiconductor manufacturing and integration techniques to build those optical functions at chip scale.

Silicon photonics is not the fiber. It is the chip technology that helps electrical systems create, control and receive optical signals.

Quick Answer

electrical data
↓
optical engine converts it to light
↓
fiber carries the light
↓
receiver converts it back to electrical data

Optics becomes attractive when very-high-speed electrical links become too difficult in power, reach or signal integrity.

Co-packaged optics (CPO) moves the optical engine much closer to the switch or compute silicon, shortening the hardest high-speed electrical path.

Why AI Needs So Much Communication

Training can split one model across many accelerators. Those devices exchange gradients, activations, parameters and synchronization data.

Inference can also move requests, KV-cache data, model state and intermediate results among machines.

If the network cannot keep up, adding GPUs produces diminishing returns.

Why Copper Does Not Simply Disappear

Copper remains inexpensive, serviceable and efficient for many short connections.

The challenge grows as data rates rise and electrical paths become longer. Signal loss increases, and equalization, retimers and DSPs consume additional power to recover the signal.

So the practical question is not “Is optics better than copper?”

It is: at this bandwidth, distance, density and power budget, which link is better?

Original Asset 1: The Connectivity Distance Ladder

on-die → package → board → rack → row → data center → data center to data center

Electrical links dominate many of the shortest connections. Optics has long dominated longer ones.

What AI changes is the boundary: higher bandwidth density and power pressure push optics closer to switches and eventually toward compute.

There is no universal crossover distance.

What Is Pluggable Optics?

Most data-center optical links today use removable modules at the front of switches.

The switch ASIC—the main switching chip—sends high-speed electrical data across the board to the module. The module converts the data into light.

This is operationally convenient because a failed module can be replaced independently.

But as speeds rise, the electrical path between ASIC and front panel becomes expensive to drive.

Original Asset 2: The Electrical-to-Optical Conversion Tax

Pluggable path:

ASIC → longer electrical trace → retimer / DSP / equalization → optical module → fiber

CPO direction:

ASIC → very short electrical path → optical engine → fiber

CPO does not eliminate electrical-to-optical conversion. It reduces the difficult electrical distance before conversion.

What Is Co-Packaged Optics?

CPO places optical engines next to the switching or computing silicon, on the same package or immediately adjacent to it.

Broadcom describes this as a way to reduce path loss and the DSP burden caused by longer high-speed electrical traces.[4]

2026 Is Different: CPO Is Moving Into Production

NVIDIA says Spectrum-X Ethernet Photonics integrates CPO with the switch ASIC and reaches up to 409.6 Tb/s of aggregate switch bandwidth. Its May 2026 Vera Rubin announcement says the photonics platform is in production.[2][3]

Broadcom also says it is shipping production CPO systems and offers 200G-per-lane technology and a 102.4-Tb/s CPO switch family.[4]

The question is therefore moving from “Can CPO work?” to “Can it scale economically and operationally?”

Silicon Photonics Itself Is Already a Volume Technology

Intel says its silicon-photonics platform has shipped more than 8 million PICs and more than 32 million on-chip lasers since 2016.[1]

Intel's current portfolio includes 400G, 800G and 1.6T products. Its first-generation Optical Compute Interconnect chiplet supports 4 Tb/s bidirectionally and is designed for co-packaging with CPUs, GPUs and other SoCs.[1]

So the bottleneck thesis is not “we do not know how to make silicon photonics.”

It is whether the entire optical-engine supply chain can scale as fast as AI-network demand.

Original Asset 3: The Photonics Bottleneck Stack

laser source
↓
photonic integrated circuit
↓
electrical IC / DSP
↓
advanced packaging
↓
fiber attachment
↓
test & yield
↓
cooling
↓
field service

A finished CPO system is limited by the weakest layer in this chain.

The Laser Is a Separate Engineering Decision

Different vendors use different light-source architectures.

Intel emphasizes integrated on-chip lasers.[1]

Other CPO architectures can use external or pluggable continuous-wave laser sources, which may keep the laser away from the hottest silicon and allow different replacement strategies.

There is no single universal architecture.

Moving Optics Closer Creates a Thermal Tradeoff

Pluggable optics sits away from the hottest switch ASIC. CPO deliberately moves optics closer.

That reduces the electrical-distance problem but creates a tighter thermal and packaging problem.

NVIDIA's Quantum-X photonics switch, for example, uses a liquid-cooled design for onboard silicon photonics.[2]

Moving optics closer solves one electrical problem while making thermal integration more demanding.

Serviceability Is Also Part of the Architecture

A pluggable optical module can be removed in the field.

CPO integrates more optics into the switch package, so operators care about failure isolation, laser replacement, fiber handling, repair time, spare strategy and how much hardware must be replaced after one optical failure.

The fact that major vendors now emphasize resiliency and serviceability shows that deployment is not only about bandwidth per watt.[2][4]

TSMC Shows Why Photonics and Packaging Are Converging

TSMC's COUPE technology is designed to integrate silicon photonics with electrical control chips through its 3D-integration ecosystem.

TSMC's 2025 annual report said volume production was expected in 2026.[8]

However, its June 2026 shareholder-meeting materials still described COUPE among technologies being developed.[9]

So this rebuild does not assume that a broad full-volume ramp has already been completed.

Where Could the Actual Bottleneck Form?

TrendForce said in July 2026 that NVIDIA and Broadcom had begun ramping CPO switches and identified optical-engine yield and advanced-packaging capacity as important constraints on expansion.[10]

The constraint may not be the ability to send data with light. It may be the ability to manufacture, package, test and service enough reliable optical engines.

Original Asset 4: The Optical Capacity Equation

deployable optical capacity
≈
min(PIC output,
laser capacity & reliability,
EIC / DSP supply,
advanced packaging,
fiber-attach & test throughput,
usable yield,
serviceable system capacity)

This is a conceptual diagnostic, not an industry formula.

Pluggable Optics Is Still Improving

CPO is not competing with a frozen alternative.

Marvell says its 1.6T Ara optical DSP is shipping in mass volume, and in September 2026 it demonstrated technology aimed at 400G per lane and future 3.2T optical connectivity.[6][7]

For some links, improved pluggables may remain the better answer. For very dense, power-constrained fabrics, CPO may become more attractive.

A Short Speed Decoder

200G per lane means one lane carries about 200 gigabits per second.

1.6T module means the complete optical module carries about 1.6 terabits per second.

102.4T or 409.6T switch refers to aggregate switching capacity across many ports and lanes.

Original Asset 5: The CPO Adoption Test

  1. Electrical pain: Is current electrical reach consuming too much power or signal margin?
  2. Density: Is bandwidth density high enough to justify integrated optics?
  3. Power: Does lower power per bit offset package complexity?
  4. Yield: Can optical engines be manufactured at high enough yield?
  5. Laser: Is the light source reliable and serviceable?
  6. Assembly: Can fiber attach and test scale economically?
  7. Operations: Can failures be repaired without unacceptable downtime?
  8. Alternative: Is pluggable optics or copper still good enough?

So Could Silicon Photonics Really Become the Next Bottleneck?

Yes—but the phrase needs precision.

A meaningful bottleneck forms if demand for deployable optical engines grows faster than the industry's ability to produce reliable finished systems.

The shortage could appear in PICs, lasers, electrical control silicon, packaging, fiber attach, test, yield or service architecture.

So “silicon-photonics bottleneck” is often shorthand for a broader optical-integration bottleneck.

What to Watch Next

  1. CPO deployment beyond initial production/ramp.
  2. Primary evidence of broader TSMC COUPE production.
  3. Optical-engine yield.
  4. Advanced-packaging capacity.
  5. Integrated vs external laser architectures.
  6. How long 1.6T pluggables remain competitive.
  7. The move toward 3.2T optical connectivity.
  8. How close optics moves toward compute and memory I/O.

The Simple Idea to Remember

AI scale is a compute problem and a data-movement problem.

The real silicon-photonics challenge is turning light into a reliable, manufacturable and serviceable part of the AI machine.

Key Vocabulary

fiber
The glass medium that carries optical signals.

laser
The light source used by an optical communication system.

optical transceiver
A device that converts electrical data to optical signals and back.

photonic integrated circuit (PIC)
A chip that integrates optical functions such as modulation, routing and detection.

silicon photonics
Silicon-based semiconductor manufacturing and integration used to build photonic systems.

pluggable optics
Replaceable optical modules installed in switch or server ports.

co-packaged optics (CPO)
Optical engines placed next to switch or compute silicon to shorten high-speed electrical links.

SerDes
Circuitry that converts parallel data to high-speed serial data and back.

DSP
Digital signal processing used to recover or condition high-speed signals.

Read the AI Hardware Full Stack Series

  1. Why AI Chips Need Advanced Packaging, Not Just Smaller Transistors
  2. What Is a Chiplet? Why AI Chips Are Splitting Into Specialized Dies
  3. Why Silicon Photonics Could Become the Next AI Data Center Bottleneck
  4. What Is an NPU? Why AI Does Not Have to Run Only on GPUs
  5. The Hidden Chips Behind AI Power: Why Power Semiconductors Matter

Related Articles

Sources

  1. Intel — Silicon Photonics, checked October 4, 2026.
  2. NVIDIA — Silicon Photonics Networking, checked October 4, 2026.
  3. NVIDIA — Vera Rubin ramps into full production, May 31, 2026.
  4. Broadcom — Co-Packaged Optics, checked October 4, 2026.
  5. Broadcom — OFC 2026 AI infrastructure optics, March 12, 2026.
  6. Marvell — 1.6T optical DSP portfolio, March 12, 2026.
  7. Marvell — ECOC 2026 optical technology demonstrations, September 20, 2026.
  8. TSMC — 2025 Annual Report / COUPE.
  9. TSMC — 2026 AGM Minutes, June 4, 2026.
  10. TrendForce — CPO volume ramp and expansion constraints, July 27, 2026.

Sources checked through October 4, 2026. Vendor performance and efficiency figures are attributed to their publishers. Silicon photonics, pluggable optics, CPO and electrical interconnects can coexist; the best architecture depends on bandwidth, distance, power, cost, reliability and serviceability.